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1 W A Alpaugh and J M McCreary, IPC-TP-108, Fall Meeting, 1976 2 R R Tummala and S Ahmed, Overview of Packaging for the IBM Enterprise System 9000 Based on the Glass-Ceramic Copper/Thin Film Thermal Conduction Module, IEEE Trans on Comp, Hybrids and Mfg Tech, Vol 14, No 4, Dec 1991, pp 426 431 3 L E Thomas, et al, Second-Level Packaging for the High End ES/9000 Processors, IBM J of Research & Development 4 H Murano and T Watari, Packaging Technology for the NEC SX-3 Supercomputers, IEEE Trans on Comp, Hybrids and Mfg Tech, Vol 15, No 4, Aug 1992, pp 411 417 5 A Takahashi, et al, High Density Multilayer Printed Circuit Board for HITAC M-880, op cit, pp 418 425 6 Clyde F Coombs, Jr (ed), Printed Circuits Handbook, 3d ed, McGraw-Hill, New York, 1986, Chap 13 7.

A l Heat input Tank -

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US Patent 2,938,805, 1960 8 US Patent 3,628,999, Dec 1971 9 US Patent 3,799,802, Mar 1974 10 US Patent 3,799,816, Mar 1974 11 US Patent 3,600,330, Aug 1971 12 Japanese Patent 43-16929, July 1968 13 Japanese Patent 58-6319, Feb 1983 14 H Steffen, Additive Process, Ruwel Werke GmbH, private communication 15 K Minten and J Toth, PWB Interconnect Strategy Using a Full Build Electroless Plating System: Part I, PC World Conference V, Paper No b-52, Glasgow, Scotland, June 1990 16 K Minten, J Seigo, and J Cisson, Part 2: Etch Characteristics, Circuit World, Vol 18, No 4,Aug 1992, pp 5 12 17 K Minten and J Cisson, Part 3: Characterization of a Semi-Additive Naked Palladium Catalyst, Circuit World, Vol 19, No 2, Jan 1993, pp 4 13 18 K Minten, K Kitchens, and J Cisson, Part 4: The Future of FBE Process, private communication 19.

N Ohtake, Electronics Technology (Japanese), 27(7), June 1985, pp 55 59 20 N Ohtake, New Printed Wiring Boards by a Partly Additive Process, PC World Conference IV, Tokyo, Paper No 44, June 1987 21 S Imabayashi, et al, Partly-Additive Process for Manufacturing High-Density Printed Wiring Boards, IEEE Trans 0569-5503/92/0000-1053, 1992 22 H Akaboshi, A New Fully Additive Fabrication Process for Printed Wiring Boards, IEEE Trans on Comp, Hybrids and Mfg Tech, Vol CHMT-9, No 2, June 1986 23 R Enomoto, et al, Advanced Full-Additive Printed Wiring Boards Using Heat Resistant Adhesive, PC World Conf V, Paper No B6-1, Glasgow, Scotland, June 1990 24 K Ikai, Full Additive Boards, Electronic Materials (Japanese), Oct 1993, pp 58 63..

Thermocouple 4 T FIGURE l-11

Just as the name implies, MCM technology mounts multiple, unpackaged ICs (bare die), along with signal conditioning or support circuitry such as capacitors and resistors, to form a system, or a subsystem on a single substrate.1 In fact, in the late 1980s and early 1990s, MCMs were considered to be the ultimate interconnect and packaging solution, capable of meeting every challenge of the electronics industry. This technology placed ICs in close proximity to each other, thereby enhancing system performance by reducing interconnect delay.15 Size is often the primary driver for MCM-based systems. The typical multicomponent discrete assembly provides a silicon-to-board efficiency of <10 percent (actual total die area versus the total printed circuit board area). MCM technology can often increase the silicon-to-board efficiency to 35 or 40 percent with chip and wire assembly processes, and to 50 percent or higher with some of the higher-density processes.16 Thus, with reduced size and weight, MCMs offer a practical approach to reducing overall system size while providing enhanced performance due to a reduction in the interconnect distance between chips.1 Multichip modules typically use three to five times less board area than their equivalent discrete solution.16

Since a multichip module is, by definition, a single substrate containing two or more ICs, it is unlikely that they are a thing of the past. Instead, they have been renamed from MCMs to MCPs, few chip packages (FCPs), or other similarly descriptive names. These packaging solutions usually contain from about two to six ICs that are packed onto an inexpensive laminate substrate. Although they are multichip modules, they may be called something else. Intel refers to its twochip package as a CSP, although in fact it is an MCP or MCM .17 Interestingly, some still believe that when time is an important consideration while reaching the market with a low-cost and reliable product, multichip solutions win. On the other hand, others believe that it s only a matter of time before SOCs take over completely and multichip packaging will not be necessary, and they view multichip solutions only as stopgaps.18 Nevertheless, regardless of their nomenclature, laminate based multifunctional packages are among the key package types in the industry.

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